Interrupts and bus accesses

From: Marko Mäkelä (
Date: 2001-07-26 14:32:53

On Thu, 26 Jul 2001, Ruud Baltissen wrote:

> That must be centuries ago....

Nope, only some years ago.

> Anyway I seem to remember that you (?) wrote that data was written to the
> stack during a reset. Using my debugger I found out that the R/W-line
> remained (H) so there is no write-action.

But I clearly remember that there were 2 or 3 accesses to $01xx.  
Probably the R/W line has been intentionally disabled during the RESET
sequence, so that systems that map I/O to the $01xx area cannot do stupid
things when they are powered on.  The contents of the S register could be
anything after a power-on reset.

> Hmmm, this means that the CPU UT will be a 65816, switching to a 6510
> again is a little difficult.

Then the results would not confirm anything.  I remember reading from
either the WDC 65816 or the Rockwell 65C02/102/112 data sheet that the
reset sequence there would last 6 cycles.

> Just a question: why do the 65xx processors behave like this ie. doing 7 (?)
> cycles of "nonsense"? The Z80 and 80x86 start up with their reset-address
> without any "unneeded" actions.

Instead, they do "unneeded" actions such as RAM refresh on each clock
cycle. :-)  The main reason probably is that the 65xx uses a RESET vector,
while the Z80 and the 80x86 and some other architectures (Atmel AVR to
name a modern one) use a jump table.

The designer(s) probably shared the same gates or transistors for all
interrupt logic (RESET, NMI, IRQ and BRK).  Since a 65xx processor is not
reset so often in normal applications, paying a 5-cycle extra penalty
shouldn't be that bad.  And I think the 2 first cycles are necessary
anyway to simplify the instruction fetch pipeline logic.  So, there
actually are only 3 unnecessary cycles, the disabled stacking of the
program counter and the processor status flags.

Does anyone have good ideas why the 6502 ignores its RDY input during
write cycles?  Or is the line actually ignored?  Has anyone made any
experiments with it?  (This alleged feature is the reason why the video
chip initiates forced DMA sequences 3 cycles in advance.  The 6502 can
wriet at most 3 times in succession, when executing the interrupt


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