> Then the results would not confirm anything.
I decided to hack this C64 by cutting the inputpin towards the expansionport
of the AND-gate dealing with the RDY-input. Then I can test everything with
a 6510. OK ? :)
> Does anyone have good ideas why the 6502 ignores its RDY input during
> write cycles? Or is the line actually ignored? Has anyone made any
> experiments with it?
Yep. I ones had problems with a circuit and suspected the data written to
it. So I added a switch to my debugger which froose the latches after the
next cycle. In this way I trapped the first byte and address of every
action. Releasing the switch then showed the actual data and address on the
bus again. This simply proofed that the 6510 that the 6510 did not halt
during a write cycle.
For the why, I haven't the faintest idea. Ask the guy who designed it. The
docs say this allows the CPU to read slow devices. I always wondered how
these slow devices then suddenly could cope with "fast" write actions.
___
/ __|__
/ / |_/ Groetjes, Ruud
\ \__|_\
\___| http://Ruud.C64.org
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