Re: C-128 and Jeri board

From: john/lori (
Date: 2001-05-02 18:46:31

> > 
> > I'd go for a new motherboard as well, provided I can fit it into my C128
> > Tower case ;-)
> Hey bogax, How about submitting our ideas? :)

I have no objection, I think I'd like to hear them myself :)

I'd just point out that, at this point it's all talk
(unless you've gotten a lot farther than I have)

Presumably they all know what talk is worth.

The idea is, basically, a baby AT form mother board to take
the chips from a C64, with the idea of moving to bigger and
better things eventually, and including some enhancements.
enhancements that would be included intially would be:

16 bit ISA bus

multiple cartridge ports

integrated expansion RAM

seperate RAM for the VIC

some sort of fast "serial" bus (ie something to serve the same
 function as the C64 serial bus, but faster, this would be in
 addition to or an enhancement of the serial bus)(Nate favors SCSI)

bigger and better things would be stuff like:

VIC compatible VGA (I don't envision anything as elaborate as what
 Jeri's doing, I'd prefer 800x600 but I'd settle for 640x480 with
 256 colors)

16 bit CPU (jbev wants 65816, no doubt that would be easiest,
 but I'm ambivalent.  I'm not interested in getting tied to
 proprietary hardware)

Everything in programmable logic

So jbev, what did I leave out?

I'll just speculate breifly on RAM expansion (since that's what
I've been thinking about just recently).

Initially I had thought to start with an 8 bit to 16 bit memory
mapper in discrete logic.  This would be something that could
be pieced together out of junk (mostly) (stuff from a couple
of old mother boards) and fit the cartridge port on the C64
Basically using UMAX to map in memory upto 16 meg in 256 byte
pages with a rudimentary DMA capability for swapping the bottom
4K (mostly for zero page and the stack, probably no more than
256 bytes at a time)

Mapping would be done with 32K cache chips, and allow you to
map the maps ie you set up a bunch of 56K maps (64K minus
the bottom 4K and IO) and then select maps with a single byte.

DMA would use a single presettable 8 bit bi directional counter
that stopped on roll over.

Initially it would only support 4 and 8 meg 72 pin simms

Later the scheme would be integrated with a full blown REU
compatible, 16MB DMA capability (jbev wants multi gigabytes
and memory protection) and incorprated on the new mother board
(at which point DMA for swapping zero page becomes moot)

Now I'm wondering if it doesn't make more sense just to go
straight to an integrated mapper and REU style DMA controller,
in CPLDs.

I'm also wondering what the unused spots in the memory map
(those locations in the SRAM that correspond to the bottom
4K and IO) could be used for. (DMA reload registers comes
to mind)

Also trying to decide how to fit in gobs of IO in the most
compatible way possible.

A discrete version of the mapper would take 40-50sq" of board
and a lot of soldering and wouldn't do much in the way of
usefull DMA. Any savings from using junk would be offset by
the additional cost of the board, if nothing else, but junk
is more accessable.  

Plus I think you could fit in fast memory to memory DMA in the
expansion memory (eg 32 bits wide at the dotclk rate)

Besides, Watson wants an REC done NOW ;)

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