Hallo Per, > If you have a way of intercepting write cycles to memory it shouldn't > be too hard to implement mirroring. This way the CPU will read at X > MHz and write a 1 MHz, running at full speed most of the time. Why didn't I think of that myself? That is a very good solution indeed !!! A small addition: include the I/O area as well. > gb> This triggered another question: the 65816 can run on 20 MHz. The > gb> SIMMs SCPU uses ar mostly of the 70 ns type. 20 Mhz means 25 ns > gb> cycles. How does that fit? > > Wait states. I don't have the numbers with me, but access to SuperRAM > can take several cycles. I thought of waitstates as well. A Z80 or 8088 needs several clockcycles to perform a one-byte instruction. With these CPUs it makes sense to stretch the cycle which actually accesses the memory or I/O. But the 6502 accesses the memory every cycle of an instruction. With 70 ns the 65816 has to insert 1 waitstate for every instruction. The effect is 10 MHz. But if you run it at 10 MHz, you have a 50 ns. cycle and you would still need a waitstate. With 6.666 Mhz you don't need waitstates but this is slower then the 20 MHz "10 Mhz". The above occured to me at the moment I was going to answer that it is nonsense to run it at 20 MHz. The above proves that it is sometimes very usefull to discuss things. I certainly learned something of it. Groetjes, Ruud http://Ruud.C64.org/ - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
Archive generated by hypermail 2.1.1.