>>>>> "gb" == g baltissen <g.baltissen@hccnet.nl> writes:
gb> Hallo Per,
MV> If you have a way of intercepting write cycles to memory it
MV> shouldn't be too hard to implement mirroring. This way the CPU will
MV> read at X MHz and write a 1 MHz, running at full speed most of the
MV> time.
gb> Why didn't I think of that myself? That is a very good solution
gb> indeed !!! A small addition: include the I/O area as well.
Yup, and you'll want to mirror the ROMs to RAM, and this is what the
SuperCPU does in bank 1.
gb> But the 6502 accesses the memory every cycle of an instruction.
I don't think the 65c02 or 65c816 do, but I'm not sure.
gb> With 70 ns the 65816 has to insert 1 waitstate for every
gb> instruction. The effect is 10 MHz. But if you run it at 10 MHz,
gb> you have a 50 ns. cycle and you would still need a waitstate. With
gb> 6.666 Mhz you don't need waitstates but this is slower then the 20
gb> MHz "10 Mhz".
As someone else pointed out, you're addressing 32-bit memory. Sequen-
tial reads within a row (2-8 kB) only take 1 cycle. Non-sequential
reads within the same 32-bit word always take 1 cycle. Check the link
Nate posted for the full details.
--
___ . . . . . + . . o
_|___|_ + . + . + . . Per Olofsson, konstnär
o-o . . . o + MagerValp@cling.gu.se
- + + . http://www.cling.gu.se/~cl3polof/
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