Article PC-card

From: Ruud Baltissen (
Date: 2001-02-22 13:06:31

Connecting a PC-card to a C64.

In 1988 I realised an interface for the C64 which enabled me to use PC-card.
The first use I had in mind was connecting a MFM-harddiskcard to the C64.
The project failed due to the fact that I had to write my own program for
the controller. In those days every controller had its own program fitted in
an EPROM. After some weeks my controller died (in the PC of my company) and
all work was for nothing as I could not use it for the next controller.
Having the interface, I started to use it in combination with a MGP- and a
Multi-I/O-card. The first one enabled me to use a 80 columns screen and
printerport. The second one to use fast speed RS232 and the floppydrive. I
did some trials with the drive but when I started to use PC-Disk 1.0, I
prefered to spend my time on other projects.

First have a look at the pinouts of the 8-bits ISA BUS:

Pin   Signal      Description                                   Direction
A1   -I0CHCK     I/0 channel check                              In
A2   SD7         Data  bit  7                                   In/Out
A3   SD6         Data  bit  6                                   In/Out
A4   SD5         Data  bit  5                                   In/Out
A5   SD4         Data  bit  4                                   In/Out
A6   SD3         Data  bit  3                                   In/Out
A7   SD2         Data  bit  2                                   In/Out
A8   SD1         Data  bit  1                                   In/Out
A9   SDO         Data  bit  0                                   In/Out
A10  -I0CHRDY    I/0 Channel ready                              In
Al1  AEN         Address enable                                 Out
A12  SA19        Address   bft   19                             Out
A13  SA18        Address   bit   18                             Out
A14  SA17        Address   bit   17                             Out
A15  SA16        Address   bit   16                             Out
A16  SA15        Address   bit   15                             Out
A17  SA14        Address   bit   14                             Out
A18  SA13        Address   bit   13                             Out
A19  SA12        Address   bit   12                             Out
A20  SA11        Address   bit   11                             Out
A21  SA1O        Address   bit   10                             Out
A22  SA9         Address   bit    9                             Out
A23  SAS         Address   bit    8                             Out
A24  SA7         Address   bit    7                             Out
A25  SA6         Address   bit    6                             Out
A26  SAS         Address   bit    5                             Out
A27  SA4         Address   bit    4                             Out
A28  SA3         Address   bit    3                             Out
A29  SA2         Address   bit    2                             Out
A30  SA1         Address   bit    1                             Out
A31  SA0         Address   bit    0                             Out

B2   RESET DRV   Active high reset                              Out
B3   +5Vdc
B4   IRQ2        Interrupt request 2                            In
B5   -5Vdc
B6   DRQ2        DMA request 2                                  In
B7   -12Vdc
B8   -CARD SLCTD Card selected                                  In
B9   +12Vdc
B11  -MEMW       Memory write                                   Out
B12  -MEMR       Memory read                                    Out
B13  -IOW        I/O write                                      Out
B14  -IOR        I/O read                                       Out
B15  -DACK3      DMA acknowledge 3                              Out
B16  DRQ3        DMA request 3                                  In
B17  -DACK1      DMA acknowledge 1                              Out
B18  DRQ1        DMA request 1                                  In
B19  -REFRESH    Refresh                                        Out
B20  CLOCK       System clock                                   Out
B21  IRQ7        Interrupt request 7                            In
B22  IRQ6        Interrupt request 6                            In
B23  IRQ5        Interrupt request 5                            In
B24  IRQ4        Intertupt request 4                            In
B25  IRQ3        Interrupt request 3                            In
B26  -DACK2      DMA acknowledge 2                              Out
B27  T/C         Terminal count                                 Out
B28  ALE         Address latch enable                           Out
B29  +5Vdc
B30  OSC         Clock 14.31818Mhz                              Out

IOCHCK is an active (L) signal meant to signal the PC that there is a memory
parity error. On the end this signal triggers the NMI-input of the CPU. As
so we can use the NMI-input of the expansionport.

SD0..7 is connected to D0..7.

IOCHRDY signals the CPU that the card needs more time for whatever it is
doing. This is realised by holding the CPU. The 6510 has such a feature as
well but the problem is that the corresponding input can be found at the
expansionport. To be honest, I never saw a card having this line. I did not
use this line.

AEN tells a card that an (H) and the use of the I/O lines means there is a
DMA transfer in progress. As the C64 has no DMA capabilities onboard, we can
tie this line to GND. But I thinking of the idea of adding a 8237
DMA-controller to a C=. So in the future....

A PC-card uses 20 addresslines but the C64 only has 16. And to make it
worse, we only have a range of 512 free to use for our own purposes. In 1988
I hacked my C64 by de-mirroring the VIC and SID, freeing 1.5 KB. I used 512
bytes for my interface. Why only 512? To remain compatible with users who
didn't want to hack their C64. The idea was to use 256 bytes for the swap
area and to reserve a part of the other 256 bytes for I/O.
The above meant that I needed to provide another 12 addresslines using
buffers. In 1988 I used two 74LS374s. No read back possebility (less
soldering, used RAM).

RESET DRV is an active (H) reset signal. Generated by using the resetline of
the C64 thru a 7406.

IRQ2..7 are active (H) interrupt inputs. I ORred these signals and connected
them to the IRQ-input thru a 7406. I also connected them to a 74LS541 to
determine which IRQx was activated.

MEMR, MEMW, IOR, IOW. The INTEL and ZILOG CPUs sepperated I/O and memory
handling. But they also used these lines to inform connected IC's when data
was valid or not. The 65xx uses CLK2 for this purpose. I made the difference
between I/O and memory by using bit 7 of the 374 used to generate A16..19. I
used a 74LS138 to generate the needed signals:
A   - CLK2
B   - bit 7
C   - R/W
/G1 - IO2
/G2 - IO2
G   - BA
Y0..3 -> no meaning
Y4 -> MEMW
Y5 -> MEMR
Y6 -> IOW
Y7 -> IOR

DRQx, DACKx, REFRESH, T/C and ALE not used in the 8 bits version.

CLOCK: I connected CLK2 to it.

Some remarks are at the end.

In 1989 I made a 64 KB SRAM card to use in an AT. This enabled me to use
more memory in a simple way. I also got interested in using memory expansion
cards for the C64. So I started to make a 16 version.

16-bit AT extension
C1   SBHE        System bus high enable                         In/Out
C2   LA23        Address bit 23 (unlatched)                     In/Out
C3   LA22        Address bit 22 (unlatched)                     In/out
C4   LA21        Address bit 21 (unlatched)                     In/Out
C5   LA20        Address bit 20 (unlatched)                     In/Out
C6   LA19        Address bit 19 (unlatched)                     In/Out
C7   LA18        Address bit 18 (unlatched)                     In/Out
C8   LA17        Address bit 17 (unlatched)                     In/Out
C9   -MEMR       Memory read                                    In/Out
C10  -MEMW       Memory write                                   In/Out
C11  SD08        Data bit 8                                     In/Out
C12  SD09        Data bit 9                                     In/Out
C13  SD10        Data bit 10                                    In/Out
C14  SD11        Data bit 11                                    In/Out
C15  SD12        Data bit 12                                    In/Out
C16  SD13        Data bit 13                                    In/Out
C17  SD14        Data bit 14                                    In/Out
C18  SD15        Data bit 15                                    In/Out
D1   -MEM CS16   Memory 16-bit chip select                      In
D2   -I/O CSI6   I/O 16-bit chip select                         In
D3   IRQ10       Interrupt request 10                           In
D4   IRQ11       Interrupt request 11                           In
D5   IRQ12       Interrupt request 12                           In
D6   IRQ15       Interrupt request 13                           In
D7   IRQ14       Interrupt request 14                           In
D8   -DACK0      DMA acknowledge 0                              Out
D9   DRQO        DMA request 0                                  In
D10  -DACK5      DMA acknowledge 5                              Out
D11  DRQ5        DMA request 5                                  In
D12  -DACK6      DMA acknowledge 6                              Out
D13  DRQ6        DMA request 6                                  In
D14  -DACK7      DMA scknowledge 7                              Out
D15  DRQ7        DMA request 7                                  In
D16  +5Vdc
D17  -MASTER     Used with DRQ to gain control of system        In
D18  Ground

SHBE signals the card wether an 8 or 16 bits transfer is in progress. Used
bit 6 of the above 374.

The AT-extension provides 4 extra addresslines. 16 MB was such a enormous
amount of memory those days, that I only provided A20..21 using the left
over bits of the 374 mentioned above. Otherwise I had to add an extra 374
just for the IO/MEM differentiation and SHBE.

The expansion as MEMx signals as well. In AT the original MEMx signals are
only active when addressing the range up to $10000. I used some OR-gates and
an invertor to determine if the address was in this range and mixed this
signal with the MEMx signals for the 8-bit part using OR-gates.

IRQ10..14: added an 541 plus logic to activate IRQ

DRQx, DACKx, MASTER: not used.

D8..15: The trick I used here I later used with my IDE-interface. I added
added two 74ALS573s. One was used to store the data form the C64 towards
D8..15. The data was outputted during _every_ write action. The other 573
was used for the opposite direction. Here the data was only stored during a
read action of the PC-card.

I/O CS16, MEM CS16: not used as the only had an function for the internal of
a PC. Reading/writing a WORD from/to an 8-bits card implies that the
_HARDWARE_ (and _not_ the CPU) performs two 8 bit reads/writes from/to the
card. These lines signaled the hardware that the card was able to deliver 16
bits at once and no tricks were needed.

Remark: writing a BYTE to an odd address of an 8-bits card resulted writing
the byte to D0..D7. With a 16-bits card this resulted in writing to D8..15.
I thought about implementing this as a HW-feature, but as I had to write the
software for any card all myself any way, I prefered the SW-solution. My
risk: if I changed a 8-bit card for an 16-bit version, I had to rewrite the
SW for this card. The only cards I had in mind anyway were a
memory-expansion-card and AT-harddiskcard.

I have little experience with this card as in 1991 I was scheduled to go to
Kouwait. So I packed my things to be stored for the time being there. Only
to see a big hole in wall of our office on television the day before my
flight, Saddam probably didn't like the furniture :( Anyway, only after
finding a new appartment, I found out a box was missing. Two of the things
in that box were the above cards :((((

Remarks regarding the hardware:
As mentioned I used 574s for the cards. Nowadays I would use 6526 as I have
enough of them. Soldering two 574s means soldering 40 pins. Soldering a 6526
(or 6821) means 40 pins as well but the advantage is readback facility and
some extra lines.

Groetjes, Ruud

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