Re: MOS process details?

There's been a couple recent long interviews with those guys, including Al Charpentier. He may
respond to questions in recent times.

I am sure they are on Youtube. 

-Pete

January 12, 2023 1:44 PM, "Nate Lawson" <nate_at_root.org> wrote:

> I’m interested in the history of MOS and their processes used for various chips from calculators up
> through Amiga. I’ve read all the various books but I haven’t seen a list of their fab capabilities
> and which C= chips were made with each.
> 
> Apparently SID was 7 micron but VIC was 5 micron? What was the channel length? How did HMOS change
> this? Did they ever go to multiple metal layers? What was the wafer size and limitations? How did
> they use Applicon and CAD tools on each generation of chip? How did their processes compare to
> competitors at the time like Intel and TI?
> 
> Let me know if someone has more background on all this.
> 
> Thanks,
> Nate