Re: 6510 I/O port as chip selects to expand memory

From: Jim Brain <brain_at_jbrain.com>
Date: Thu, 18 Nov 2021 16:32:11 -0600
Message-ID: <c34631ca-eae4-560d-bbf7-723f02dad816_at_jbrain.com>
On 11/18/2021 4:02 PM, Claudio Sánchez wrote:
> El 18/11/2021 a las 21:48, Jim Brain escribió:
>> On 11/18/2021 12:59 PM, Claudio Sánchez wrote:
>>>>
>>>
>>> Why didn't you added lines 6 and 7? It wouldn't had hurt...
>>
>> Because the goal of the project was the emulate the 6510.  If you 
>> want 6/7, you can simply tweak the Verilog and put two extra pads on 
>> the design.
>
> Ok, understood then. Thanks.

I *think* I implemented the 2 extra bits in the Verilog, though they do 
not connect to anything off IC.  As, I recall, the 65XX on board IO 
ports are all there, just not bound to external pins, so you need to 
implement the DDR and the data value, as someone *could* use the IO port 
or DDR port as a general purpose memory location, and shift bits around 
on them.

Jim


>
>>
>> Jim
>>
>

-- 
Jim Brain
brain_at_jbrain.com
www.jbrain.com
Received on 2021-11-19 00:01:23

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