On Wed, 29 Jul 2020, Justin wrote: > It would be interesting to know what the clock limits would be on the > board layout itself assuming some world where you’d want to shove an > FPGA/ASIC/modern RAM/etc into the existing sockets. I doubt that the board layout will, for all practical purposes, impose clock limits to any chip replacement with respect to bus access. You'd hit the DRAM "wall" first for which the old datasheets give a read/write cycle time of 230 to 330ns depending on the speed rating (-12 to -20), limiting the safe max speed to 3MHz; a little bit over 4MHz if you want to press it. For a turbocharged plug-in system that'd result in interleaved 2MHz accesses of turbo CPU and turbo VIC if we stick to the half-cycle bus access pattern. (After all, there was a reason why turbo cards used their own memory.) Of course you could gut out the entire board, replacing *everything* on it, but I frankly wonder about the benefit of that. RainerReceived on 2020-07-29 19:00:32
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