On 7/29/20 6:04 PM, Rainer Buchty wrote: > On Wed, 29 Jul 2020, Justin wrote: > >> It would be interesting to know what the clock limits would be on the >> board layout itself assuming some world where you’d want to shove an >> FPGA/ASIC/modern RAM/etc into the existing sockets. > > I doubt that the board layout will, for all practical purposes, impose > clock limits to any chip replacement with respect to bus access. > > You'd hit the DRAM "wall" first for which the old datasheets give a > read/write cycle time of 230 to 330ns depending on the speed rating (-12 > to -20), limiting the safe max speed to 3MHz; a little bit over 4MHz if > you want to press it. Well, you could try to implement page mode which would give you more throughput. Like let VIC always grab 2 Bytes in a row unless it crosses a page border. As far as I know that's how the ULA in the spectrum does it, fetching data Byte and attribute Byte in one /RAS cycle by using page mode. GerritReceived on 2020-07-29 19:00:49
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