Re: Accessing the C64 memory between 65xx chips operations.

On 4/19/20 8:22 PM, tokafondo wrote:
> So, this is like,
> 
> "no matter how fast the DRAM is, the DRAM refresh is going to last NNN ns,
> and that is".

DRAM refresh is anormal DRAM access cycle, just with special address 
counter, VIC does 5 refresh cycles per scan line.



> "the memory access will last NNN ns, and even if the memory answers back in
> NN ns or even N ns, the VIC will wait for NNN ns to continue its tasks,
> because it doesn't check if the data has been returned but instead, it just
> expects it to be there".

That's correct. There is no signal the DRAM can use to tell the outside 
that the data is now valid. VIC expects the data to be valid at a 
certain point in the cycle. This cycle is designed to allow DRAM with a 
200ns RAS access time and have a few ns to spare. If you use a DRAM with 
100 ns, the data will just sit an extra 100ns on the bus before VIC 
samples it.

  Gerrit