Re: Accessing the C64 memory between 65xx chips operations.

From: tokafondo <tokafondo_at_gmail.com>
Date: Sun, 19 Apr 2020 13:22:40 -0500 (CDT)
Message-ID: <1587320560973-0.post_at_n4.nabble.com>
So, this is like,

"no matter how fast the DRAM is, the DRAM refresh is going to last NNN ns,
and that is". 

or

"the memory access will last NNN ns, and even if the memory answers back in
NN ns or even N ns, the VIC will wait for NNN ns to continue its tasks,
because it doesn't check if the data has been returned but instead, it just
expects it to be there".

Isn't it?



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Received on 2020-05-30 01:29:12

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