Re: Accessing the C64 memory between 65xx chips operations.

From: Gerrit Heitsch <*gerrit_at_laosinh.s.bawue.de*> Date: Sun, 19 Apr 2020 20:13:04 +0200 Message-ID: <70935874-21b3-3e17-ca45-5bc37326278e_at_laosinh.s.bawue.de> · gerrit_at_laosinh.s.bawue.de

On 4/19/20 7:53 PM, tokafondo wrote:
> And now we are talking!!!
> 
> So, the hack here would be to replace the ram chips with faster ones that
> would allow that /free/ time to appear.

You'd still need to change the timing since /RAS is generated by VIC and 
directly wired to the RAMs, nothing possible without a redesign.

> But there are not 64k x 4 DRAM chips available these days as new. But there
> are SRAM chips that are fast enough for this to happen. Would it be easy to
> adapt 5V SRAM chips there and leave VIC's DRAM refresh chips disconnected
> and that's all needed?

VIC controls all timing in the C64... I did a SRAM replacement for the 
C64 back in 2011, it works. But you're still tied to how VIC controls 
the RAM access for itself and the CPU. And since the adress lines from 
VIC are multiplexed to accomodate the DRAM, you'r stuck with that.

The better way would be the mentioned dualport RAM. See the AM2130 as an 
example. Might be hard to get though.

  Gerrit