Hello Ruud, (this is going to be a log reply....) The other answers on this topic explain generally how RAM is refreshed. There are three typical schemes, the C64 uses the simplest which is basically that the VIC-II reads the RAM using its internal counter. Every raster line 5 low-order (0-7)address lines are read (and hence refreshed) before the fetch operations are made for the character /sprite data etc. The VIC.TXT document floating on the internet explains this. 6164 chips need 7bit refreshing, 41256 need 8-bit refreshing, the 1meg chips need 9-bit refreshing etc.... The VIC-II fortunately provides 8-bit refreshing. Hence 41256's will work. (the "7bit" refers to the size refresh cycle, 128 cycles required, or pins A0-A6 have to be cycled) However, 4464 chips (or 41464) used in the C64c require 8bit refreshing, and so on +1 over the above requirements. The extra "width" of the chip requires an extra bit for cycling because the number of cells is the same in a 41464 as it is in a 41256). Hence, the C64c works with 4464 chips because of the VIC-II's A0-A7 refresh counter. Now... 30pin 256kB SIMMS unfortunately generally use two 44256 chips (and sometimes one 41256 for parity). The 1MB SIMMS use either 8 or 9 1MegaBIT chips. The problem in both cases is refresh will not work on all cells. Having given some though to this before I found several tricks the Z80 guys use to get around this problem (the Z80 has an internal 8bit refresh counter). The solution I think for the C64 is to use the BA signal (which goes low before the refresh /fetch cycles) to control a counter. The higher bits of this counter can provide higher order bits for the SIMMS, but only for the first 5cycles of BA=low). After the 5th byte, the normal "VIC page" address needs to be shown in order to fetch the correct video data. So... with a counter, multiplexer and some glue, RAM with greater than 256kilo-bits could be refreshed (btw: the time between refreshes doubles as memory size quadruples, which is very handy). I haven't done more other than develop this theory.... so I haven't got a circuit in mind. Hope this helps. Regards, Nick PS: to expand the VDC RAM to 256kB, one would use a board eight 41256 chips for this reason. -- On Thu, 18 Jan 101 19:03:35 g.baltissen wrote: >Hallo, > >I've expanded some C64's and C128's by replacing the original 4164 by >41256's. But I have some 30 pin 256 KB and 1 MB and even some loose 72 pin >4 and 8MB modules laying around. Who has experience in connecting these to >a C=? The problem is that I have no idea if the refresh used for the >4164/41256 is good enough for the bigger RAMs. I can imagine that they need >more addresslines to used during a refreshcycle. > >-- >Groetjes, Ruud > >http://home.hccnet.nl/g.baltissen/index.htm > > > >- >This message was sent through the cbm-hackers mailing list. >To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org. > Get your small business started at Lycos Small Business at http://www.lycos.com/business/mail.html - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail email@example.com.
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