Having just perused a few data sheets, I'll speculated that any 256k bit or larger chip you're likely to want to use, will have an on chip refresh counter and be capable of /CAS before /RAS refresh. Therefore, why not just supress (or modify) the normal VIC refresh cycle and do a /CAS before /RAS refresh cycle. bogax > Having given some though to this before I found several tricks the Z80 guys use to get around > this problem (the Z80 has an internal 8bit refresh counter). The solution I think for the C64 > is to use the BA signal (which goes low before the refresh /fetch cycles) to control a counter. > The higher bits of this counter can provide higher order bits for the SIMMS, but only for the > first 5cycles of BA=low). After the 5th byte, the normal "VIC page" address needs to be shown > in order to fetch the correct video data. > > So... with a counter, multiplexer and some glue, RAM with greater than 256kilo-bits could be > refreshed (btw: the time between refreshes doubles as memory size quadruples, which is very > handy). I haven't done more other than develop this theory.... so I haven't got a circuit in > mind. > > Hope this helps. > > Regards, > Nick - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tml.hut.fi.
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