Re: GO64 tech stuff?

From: Richard Atkinson (
Date: 2000-08-28 17:16:53

Here are the results of my initial TEST bit investigations.

Setting TEST seems to cause a 1 cycle delay in which the processor is
halted and the VIC makes some sort of non-standard access. It also seems
to alter the contents of the VIC's 1 line video matrix and colour nybble
at the location of the delay, though I haven't worked out where the new
data comes from yet. It is not always $FFF; sometimes $000. I suspect this
may come from main memory, since that contains 00s and FFs all over the
place after powerup.

After that, video and processor accesses continue as normal. Thus, to
remove one character line from the display there must be 7 cycles between
TEST being set and TEST being reset, not 8. It also seems to be possible
to initiate a badline using TEST (presumably due to the incremented
vertical line counter), though only during the first (halted) cycle after
TEST was set. During the period where TEST is high and the processor is
running, no badline DMA transfers are initiated even though the lowest 3
bits of RASTER can equal YSCROLL in this time.

Nicolas, does this agree with your investigations?


Richard Atkinson
Software Engineer
Tenison Technology EDA Ltd

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