On Mon, 28 Aug 2000, Richard Atkinson wrote: > Setting TEST seems to cause a 1 cycle delay in which the processor is > halted and the VIC makes some sort of non-standard access. It also > seems to alter the contents of the VIC's 1 line video matrix and > colour nybble at the location of the delay, though I haven't worked > out where the new data comes from yet. It is not always $FFF; > sometimes $000. I suspect this may come from main memory, since that > contains 00s and FFs all over the place after powerup. No, no, no. Setting test causes no such thing. It is the incrementing of RASTER itself which causes the delay, under the normal rules of BA and AEC interaction. Sort of. I have a feeling there's slightly more to it than that, but I can't work out what. Something to do with the first 3 cycles after TEST has been set. Richard -- Richard Atkinson Software Engineer Tenison Technology EDA Ltd http://www.tenisontech.com/ - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail cbm-hackers-request@dot.tcm.hut.fi.
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