On Mon, 28 Aug 2000, Richard Atkinson wrote: > After that, video and processor accesses continue as normal. Thus, to > remove one character line from the display there must be 7 cycles between > TEST being set and TEST being reset, not 8. It also seems to be possible > to initiate a badline using TEST (presumably due to the incremented > vertical line counter), though only during the first (halted) cycle after > TEST was set. During the period where TEST is high and the processor is > running, no badline DMA transfers are initiated even though the lowest 3 > bits of RASTER can equal YSCROLL in this time. Should clarify: what I meant was the screen shows three idle accesses characteristic of a forced badline, but it doesn't seem to have all the characteristics of a badline; certainly the 1 line video matrix and colour nybble buffer pointer is not incremented and the buffer filled with new data. Richard -- Richard Atkinson Software Engineer Tenison Technology EDA Ltd http://www.tenisontech.com/ - This message was sent through the cbm-hackers mailing list. To unsubscribe: echo unsubscribe | mail firstname.lastname@example.org.
Archive generated by hypermail 2.1.1.