On 16/06/2018 20:34, Spiro Trikaliotis wrote: > What about JSR (two consecutive pushes), or an IRQ, NMI or BRK (three > consecutive pushes)? Isn't that safe because the first write to the stack is followed by a further write to the stack? What circumstance do you get a write followed where the next address is going to be I/O? I kinda wonder if the descripton is wrong. Does anyone have a better example of what actually happens? "In read mode the NMOS6510/8500 will stop immediately, in write mode it will stop after the last write cycle, but not without setting its address lines to the next address! No problem if the next address is a RAM/ROM location, but big problem if this address refers to an IO chip, especially an interrupt flag register. In worst case this register is read 3 times by the frozen 6510 and 1 time after the DMA when the 6510 fetches the data"Received on 2018-06-19 11:00:04
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