On 6/12/2018 4:08 PM, Mia Magnusson wrote: > Not 100% sure how it is done, but there must be some "pause" with both > RAS and CAS high between VIC and CPU access to ram, so you shouldn't > count on having a full half period of the 1MHz clock for memory access, > but slightly less. But that maybe eqauls to CAS asserted halfway > through a 1MHz half cycle? I should have been more precise. I knew that there are two RAS/CAS cycles per 1MHz cycle (one for VIC access and 1 for CPU/VIC access). The scope shots show that on the CPU cycle, CAS occurs about 1/3 of the way into the 500MHz cycle. That means there is <300nS to perform all activities. FOr 100 or 120nS, it might work, but David's 300nS would fail for sure. In other news, I now have 64kB reads working and 64kB writes working. No compare or swap, as I will need to once again modify the state machine to add those. If there is interest, I can put my Verilog up somewhere. Jim > -- Jim Brain brain@jbrain.com www.jbrain.comReceived on 2018-06-13 08:00:05
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