> On 2018-05-07, at 00:33, Jim Brain <brain@jbrain.com> wrote: > > On 4/3/2018 12:56 PM, silverdr@wfmh.org.pl wrote: >>> On 2018-03-15, at 00:33, Jim Brain <brain@jbrain.com> >>> wrote: >>> >>> On 3/14/2018 6:10 PM, >>> silverdr@wfmh.org.pl >>> wrote: >>> >>>> Actually I want to "build" a CPLD based peripheral chip. Let's say a port like 6526 but with single port and preferably without feeding it with PHI2. >>>> >>> Here's a start (copied from working code, but I removed clock, so no guarantees on first time working): >>> >> Since the conclusion was that the best bet is to feed the chip with PHI2 anyway, maybe you could post a working one? I'll have to rewrite it into vhdl anyway... >> > Sorry for the delay. > > I posted the HDL for VIC-MIDI today to github: > > https://github.com/go4retro/VIC-MIDI > > It contains working Verilog registers you can use with PHI2 to build a VIC-like device, as per your request above. Thank you Jim. Although I (actually a friend of mine) already built the port and seem to be working well on all the simulations but this might still come in handy anyway if something becomes problematic. -- SD! - http://e4aws.silverdr.com/Received on 2018-05-07 12:00:02
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