Re: Building a 6502 peripheral - timing

From: silverdr_at_wfmh.org.pl
Date: Mon, 7 May 2018 11:27:48 +0200
Message-Id: <1BDBE691-7CE6-4E64-B6FC-C05AF95FCCA2@wfmh.org.pl>
> On 2018-05-07, at 06:25, And Fachat <afachat@gmx.de> wrote:
> 
> Sorry missed that request too.
> 
> Here is my SPI chip for the 6502 in VHDL.
> http://www.6502.org/users/andre/spi65b/index.html
> 
> Note that depending on the bus load and signal quality you have to adapt to bus ringing etc on the (assumingly) CMOS input for the CPLD/FPGA with the TTL Phi2. IIRC I used a 74ls14 schmitt trigger before the phi2 input.
> But I used it in a particularly "dirty" system. And Jim's solution is sure better anyway. So just for educational purposes.

Which is the main purpose here, thank you André!

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Received on 2018-05-07 12:02:15

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