Re: Building a 6502 peripheral - timing

Den Thu, 15 Mar 2018 00:10:38 +0100 skrev silverdr@wfmh.org.pl:
> 
> > On 2018-03-14, at 23:59, Mia Magnusson <mia@plea.se> wrote:
> > 
> >> On the wave of the recent 6509 / 6502 discussion... when building
> >> or connecting a peripheral that would allow both reading and
> >> writing, what is basically needed are the following signals:
> >> 
> >> * _CS (from address decoder)
> >> * R_W (from 6502)
> >> * D[0..7]
> >> * possibly some low address bus lines A[0..3] for example
> >> * some chips take PHI2
> >> 
> >> http://archive.6502.org/datasheets/mos_6500_mpu_nov_1985.pdf
> >> 
> >> shows timing diagrams. I wonder what would be the required timing
> >> for a peripheral without PHI2 clock input. I suspect something
> >> similar to what SRAM chips specify. Any hints as where to put
> >> attention? Like relations between _CS, R_W, ... ?
> > 
> > Somewhere on the net I've seen schematics of using 16550 UART's on a
> > C64. Although the 6510 differs slightly from a 6502, it could
> > probably be used as some kind of guide.
> > 
> > 16550 has Intel timing, it's just a fancier 8250 UART which is part
> > of the 82** family of peripheral ICs that are ment both for
> > 8080/8085 and 8088.
> > 
> > For the Intel style peripherals I think you should be careful so
> > they don't get a short read before and/or after a write. One way to
> > generate the required read/write signals is to feed R/_W, PHI2 and
> > maybe other signals to a 74*128/74*138 3-to-8/dual 2-to-4 decoder.
> > 
> > It would be easier to answer if you specify some example of what you
> > want to hook up.
> 
> Actually I want to "build" a CPLD based peripheral chip. Let's say a
> port like 6526 but with single port and preferably without feeding it
> with PHI2.

Aha! I guess that you need PHI2 or use external logic for the
combinations of PHI2 and R/_W as Jim described.

> > (SRAMs is afaik never affected by spurious short reads, so with
> > those you might get away with timing that don't work well with
> > various I/O stuff).
> 
> Sorry for being ignorant here, but what exactly are "spurious short
> reads"? Something like reading chip's own output from the bus?
 
I don't know if there is any established term. I'm refering to a
situation where select/enable signals are active when R/_W changes
state. That should ideally not happen but could anyway happen with
imperfect circuits.


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