RE: Building a 6502 peripheral - timing

Hallo Patryk,


> No, it can't. PHI2 is nowhere to connect to there so it has to be taken care of externally.

I meant: the moment you disable CS, the state of WE doesn't matter anymore. In my designs I always make sure that PHI2 is part of CS selection circuit. Using R/W could be dangerous: what if WE becomes (H) before CS? In that case a bus clash can occur, even it is just a very short time.

Regarding the use of Intel and Zilog ICs: I always use a 74LS139 to create the needed /RD and /WR signals using PHI2 and R/W as inputs.


Met vriendelijke groet / With kind regards, Ruud Baltissen

www.Baltissen.org







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