Re: Building a 6502 peripheral - timing

On 03/15/2018 09:05 AM, silverdr@wfmh.org.pl wrote:
> 
>> On 2018-03-15, at 08:44, Gerrit Heitsch <gerrit@laosinh.s.bawue.de> wrote:
>>
>> On 03/15/2018 01:33 AM, silverdr@wfmh.org.pl wrote:
>>> That would imply feeding the chip with PHI2. But memory is not fed with it and still works correctly.
>>
>> Yes, but if the memory in question is DRAM, then you have /RAS and /CAS signals that are timed correctly and they implicitly 'contain' PHI2.
> 
> True. That explains good part of the confusion.
> 
>> And if you use SRAM, then you need to use PHI2 in the decoding logic to make sure that /WE on the RAM can only go low as long as PHI2 is HIGH. Otherwise you don't need to care much since a read from the wrong address does no harm to the RAM contents.
> 
> That's known but [why] doesn't this lead to those "spurious short reads" Mia wrote about?

It might, but with an SRAM it doesn't do any damage. With SRAM you can 
even change the address lines while /CS is low, it will then dutyfully 
supply the data from the new location.



>> With a peripheral it might though, on some of them status registers change state on read.
> 
> All in all, it seems like giving it PHI2 input, even if I don't plan any timers, is the safest bet, right?

Yes, if you have the spare input use it and make life simple for yourselves.

  Gerrit