Re: Building a 6502 peripheral - timing

From: silverdr_at_wfmh.org.pl
Date: Thu, 15 Mar 2018 09:00:39 +0100
Message-Id: <C469914C-EB13-48DC-B6CB-892F305C59FE@wfmh.org.pl>
> On 2018-03-15, at 08:48, Baltissen, GJPAA (Ruud) <ruud.baltissen@apg.nl> wrote:
> 
> Hallo Gerrit,
> 
> 
>> ... to make sure that /WE on the RAM can only go low as long as PHI2 is HIGH. 
> 
> IMHO the CS input of a SRAM already does take care of that.

No, it can't. PHI2 is nowhere to connect to there so it has to be taken care of externally.

-- 
SD! - http://e4aws.silverdr.com/
Received on 2018-03-15 10:00:03

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