Re: Building a 6502 peripheral - timing

From: smf <smf_at_null.net>
Date: Thu, 15 Mar 2018 11:04:29 +0000
Message-ID: <93fc28d3-6b92-4928-81b7-24144d8f7f13@null.net>
On 15/03/2018 00:33, silverdr@wfmh.org.pl wrote:
>
> The reason I worry is because I don't fully understand how a chip with no PHI2 input doesn't "get confused" whether _CS going low means a read or write cycle. What happens when _CS goes low with R_W remaining high and THEN going low, as it seems to be the case with SRAM, when _CS comes first and then comes R_W due to external combination waiting for PHI2? Isn't this what Mia called "spurious short reads"?

It depends on the sram, this one http://www.cnic.ro/ed/ic/CY6264.pdf

Has two CE1/CE2/OE/WR that are used in different combinations and timing 
based on whether you are reading or writing.

This one https://www.alliancememory.com/wp-content/uploads/pdf/AS6C8016.pdf

Just has CE/OE/WR

When reading you set the address, enable the chip and finally signal on OE

When writing you set the address and data, enable the chip and finally 
signal on WR
Received on 2018-03-15 13:00:02

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