Re: Building a 6502 peripheral - timing

On 3/14/2018 6:26 PM, silverdr@wfmh.org.pl wrote:
>> On 2018-03-15, at 00:09, Jim Brain <brain@jbrain.com> wrote:
>>
>>> Somewhere on the net I've seen schematics of using 16550 UART's on a
>>> C64. Although the 6510 differs slightly from a 6502, it could probably
>>> be used as some kind of guide.
>> 16550 is easy (Intel bus interface)
>>
>> ~WR = !(!(R/!W) * PHI2)
>> ~RD = !(R/!W * PHI2)
> What (exactly) ~WR and ~RD mean? Other that "something" write/read related? And what about _CS?
~RD means "active low on this signal means a read activity".  ~WR is 
similar.  _CS is a separate signal on Intel ICs, so no need to worry 
about it here.  It operates the same as with 65/68XX stuff.
>
> Please bear with me, I am not sure if I make myself clear on that. The general questions are something like "How a peripheral chip should react timing-wise to the incoming signals[*], so that causes no 6502/6510 interfacing problems?". "When should it start driving databus and when to stop doing it on read cycle?". "When should it latch the data bits on write cycle?". "What should be the relation between _CS and R_W?" ...
In general, all addressing and activity signals should be stable before 
PHI2 goes high.  The 64 violates this and some things behave badly.  A 
while back, it was discussed on list why the EasyFlash and the Swiftlink 
use a 7474 to shorten the phi2 cycle to fix this.

Assuming PHI2 is the last thing to change, one should place data on the 
bus during a 65XX/68XX read cycle no sooner than PHI2 going high, and 
remove after PHI2 goes low
Same for write.  The system should latch the data at the end of the 
cycle (when PHI2 falls).

Jim