Re: Building a 6502 peripheral - timing

On 3/14/2018 6:10 PM, silverdr@wfmh.org.pl wrote:
> Actually I want to "build" a CPLD based peripheral chip. Let's say a port like 6526 but with single port and preferably without feeding it with PHI2.

Here's a start (copied from working code, but I removed clock, so no 
guarantees on first time working):

module silverdream(input _reset, input _cs, input r_w, input address, 
inout [7:0]data);

wire [7:0]ddr;
wire [7:0]port;

assign data = (_cs & r_w ? (address ? port : ddr) : 8'bz);
ioport io(_reset,!_cs & !address & !r_w, ddr, !_cs & adddress & !r_w, 
port, data);
endmodule

module ioport(input reset,input [7:0]data_in,input we_ddr,output 
[7:0]ddr,input we_port,output [7:0]port,inout [7:0]signals);

register  reg_ddr(!reset,we_ddr,data_in,ddr);
register  reg_a(!reset,we_port,data_in,port);

assign signals[0] = (ddr[0] ? port[0] : 'bz);
assign signals[1] = (ddr[1] ? port[1] : 'bz);
assign signals[2] = (ddr[2] ? port[2] : 'bz);
assign signals[3] = (ddr[3] ? port[3] : 'bz);
assign signals[4] = (ddr[4] ? port[4] : 'bz);
assign signals[5] = (ddr[5] ? port[5] : 'bz);
assign signals[6] = (ddr[6] ? port[6] : 'bz);
assign signals[7] = (ddr[7] ? port[7] : 'bz);
endmodule

module register(reset, enable, d, q);
parameter WIDTH = 8 ;
parameter RESET = 0 ;

input clock;
input reset;
input enable;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;
initial q = RESET;

always @ (posedge enable, posedge reset)
   begin
   if(reset)
         q <= RESET;
   else
        q <= d;
   end
endmodule