> On 2018-03-15, at 00:09, Jim Brain <brain@jbrain.com> wrote: > >> Somewhere on the net I've seen schematics of using 16550 UART's on a >> C64. Although the 6510 differs slightly from a 6502, it could probably >> be used as some kind of guide. > 16550 is easy (Intel bus interface) > > ~WR = !(!(R/!W) * PHI2) > ~RD = !(R/!W * PHI2) What (exactly) ~WR and ~RD mean? Other that "something" write/read related? And what about _CS? > As to the general question, I have sigrok here with the LWLA1034, and I could run a timing pull of the various signals through some steady state timing period, to show the relationships, when I next test the 6509 emu. But, I'd want someone to consider where to pull the signals and work with me. If I have to spend lots of cycles trying to determine where to test signals, it's likely to not happen. Please bear with me, I am not sure if I make myself clear on that. The general questions are something like "How a peripheral chip should react timing-wise to the incoming signals[*], so that causes no 6502/6510 interfacing problems?". "When should it start driving databus and when to stop doing it on read cycle?". "When should it latch the data bits on write cycle?". "What should be the relation between _CS and R_W?" ... * - I take that there has to be some delay of the _CS edge due to address decoding. -- SD! - http://e4aws.silverdr.com/Received on 2018-03-15 01:01:59
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