On Wed, Jun 21, 2017 at 04:40:03PM +0200, email@example.com wrote: >According to the famous document by Chris Bauer, there are three timing >variants of the VIC-II. While PAL is always 63 cycles per line, with >NTSC there can be either 64 or 65 cycles per line and I am in fact able >to reproduce the difference with -model ntsc and -model oldntsc in the >current VICE. You should have the 6567R56A and 6567R8 that I gave you, right? >The question (before I spend weekend on trial'n error counting cycles >and possibly reinventing the hammer ;-) is: do we have ane established, >reliable software method for detecting which NTSC VIC-II is installed >in the machine? I guess it must have been done multiple times by now >and used in some NTSC games/demos.. The simple way is to disable interrupts and write a loop that samples $d012, counting the cycles that go between changes. I do not know if exactly such implementation is available anywhere. Andreas Boose introduced me to an algorithm that first does a "coarse" synchronization, like this: sei lda $d012 bit $d012 bne .-2 This creates a jitter of 4+3=7 cycles, assuming that .-2 is on the same page than .+2 (the bne takes 3 cycles until the loop is exited). Then, for 7 lines, spend N_CYCLES_PER_LINE-1, sampling $d012 at the end of each iteration. Do a conditional branch to .+2 (relative offset $00) if you were ahead of the schedule. After these 7 lines, you should be in perfect sync (a deterministic number of cycles have elapsed since $d012 last changed). You should revise this algorithm so that it can somehow detect the N_CYCLES_PER_LINE, which can be 63 (PAL), 64 (6567R56A), or 65 (6569). One possibility could be to start a CIA timer after the coarse synchronization, but bear in mind that there are some differences in the CIA timer operation. I think that it is doable with the processor only. Marko Message was sent through the cbm-hackers mailing listReceived on 2017-06-21 17:04:33
Archive generated by hypermail 2.2.0.