Re: NTSC VIC-II timing

Date: Wed, 21 Jun 2017 18:48:39 +0200
Message-Id: <>
> On 2017-06-21, at 18:27, Marko Mäkelä <> wrote:
> On Wed, Jun 21, 2017 at 04:40:03PM +0200, wrote:
>> According to the famous document by Chris Bauer, there are three timing variants of the VIC-II. While PAL is always 63 cycles per  line, with NTSC there can be either 64 or 65 cycles per line and I am in fact able to reproduce the difference with -model ntsc and -model oldntsc in the current VICE.
> You should have the 6567R56A and 6567R8 that I gave you, right?

I should. Although it might be hard to quickly recall where. I still haven't entirely arranged the stuff I brought back from those two trips ;-) I shall have to find it eventually in order to test on the real hardware.

>> The question (before I spend weekend on trial'n error counting cycles and possibly reinventing the hammer ;-) is: do we have ane established, reliable software method for detecting which NTSC VIC-II is installed in the machine? I guess it must have been done multiple times by now and used in some NTSC games/demos..
> The simple way is to disable interrupts and write a loop that samples $d012, counting the cycles that go between changes.

Yes but we talk about a difference of 1 cycle per line so it seems impractical to do lots of init in order to get one cycle-exact. It should be easier to count frame cycles, where the difference is going to be orders of magnitude bigger and should not require such exact synchronisation.

> One possibility could be to start a CIA timer after the coarse synchronization, but bear in mind that there are some differences in the CIA timer operation. I think that it is doable with the processor only.

What kind of differences [if I set it to count CPU cycles]?

SD! -

       Message was sent through the cbm-hackers mailing list
Received on 2017-06-21 17:06:53

Archive generated by hypermail 2.2.0.