Re: Switchless ROMs

From: Gerrit Heitsch <>
Date: Tue, 27 Dec 2016 19:25:39 +0100
Message-ID: <>
On 12/27/2016 07:19 PM, Michał Pleban wrote:
> Hello!
> Gerrit Heitsch wrote:
>> Don't forget that CPU memory access is interleaved with VIC. So you
>> won't see an access to $FFFC immediatly followed by an access to $FFFD,
>> there will be at least one access to wherever inbetween.
> Well yes, I meant "immediately" in terms of CPU accesses (1 microsecond
> apart).
>> If you're unlucky and catch a badline there will be more...
> That might be a problem. But when the computer is reset, I presume VIC
> is is also reset to some known state?

No... VIC (and TED by the way) has no RESET pin. Once it gets power, the 
internal logic starts and will run until you remove power.

  Are there badlines after VIC is
> reset, or does it reset to a blank screen?

At power on, VIC will not display anything, so I assume the default 
state is 'display off' with background color set to black which only 
means dummy accesses but no bad lines. But since there is no RESET pin, 
any assertion of the CPU RESET pin will not phase VIC and it will 
continue with what it was doing. So there is a possibility that the CPU 
has just pulled the first byte of the RESET vector when VIC asserts RDY 
and stops the CPU for 43 cycles.


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Received on 2016-12-27 19:01:40

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