Re: DRAM refresh

From: Hegedűs István <>
Date: Thu, 13 Oct 2016 23:10:13 +0200
Message-ID: <>

I have played a lot with TED's refresh counter. The counter's enable signal 
is maintained by a latch which is triggered by the horizontal counter at 
position 296. Horizontal position 336 clears this enable signal.
Playing with hcounter and setting the right value at the right time I have 
managed to bypass this clear signal but the refresh single clock signal 
ended normally (single clock change is triggered by different hcounter 
value). The result was that refresh counter stayed on and counted while the 
CPU was running already on double clock. This way I have managed to identify 
that TED clears the refresh counter at horizontal position 431 when the 
scanline is 0 (or the refresh counting has stayed on by manipulation or TED 
stop bit is active).
As I have already written once on this forum if you halt ted by the stop bit 
normally it turns on single clock and the refresh counter will work in each 
cycle. However due to a bug refresh counter doesn't always start so if you 
hook up a logical analyzer you can see that there is no refresh. This way 
you can measure with trial how long a value is kept in ram. I have managed 
to clear the memory this way.
Other option would be my FPGATED's TEDwing which has 2x 4464 dram chips. I 
could modify the code to remove refresh at a certain time (by pressing a 
key) but still a good measure method would be needed.


-----Original Message----- 
From: Gerrit Heitsch
Sent: Thursday, October 13, 2016 4:39 PM
Subject: Re: DRAM refresh

On 10/13/2016 07:45 AM, Marko Mäkelä wrote:
> By the way, how long would the DRAM contents survive without refresh?
> Maybe it is possible to find this out on a C16 or plus/4, by 'halting'
> the TED for some time by constantly resetting one of its horizontal
> counters?

That depends on the DRAM... I remember once reading a test where the
result was that most US made DRAMs stuck pretty close to the spec.
Meaning they really needed the 128/2ms or 256/4ms while most japanese
made DRAMs kept the data much longer, some into the second range.

Also, the question is whether TED's refresh counter is coupled to the
horizontal counter or free running and just getting triggered by the
horizontal counter.


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Received on 2016-10-13 22:00:02

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