On 10/13/2016 11:10 PM, Hegedűs István wrote: > Hi, > > I have played a lot with TED's refresh counter. The counter's enable > signal is maintained by a latch which is triggered by the horizontal > counter at position 296. Horizontal position 336 clears this enable signal. > Playing with hcounter and setting the right value at the right time I > have managed to bypass this clear signal but the refresh single clock > signal ended normally (single clock change is triggered by different > hcounter value). The result was that refresh counter stayed on and > counted while the CPU was running already on double clock. This way I > have managed to identify that TED clears the refresh counter at > horizontal position 431 when the scanline is 0 (or the refresh counting > has stayed on by manipulation or TED stop bit is active). You mean that the refresh counter is cleared at a certain position instead of just rolling over? I wonder why they did that since it will produce an uneven refresh. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2016-10-14 07:00:25
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