On Thu, Oct 13, 2016 at 10:11:59PM +0200, Gerrit Heitsch wrote: > >>Doing 5 refresh cycles per scanline will take 51 scanlines to read all > >>256 addresses. > > > >This is about 3ms btw, so 2ms DRAMs shouldn't work well at all. > > Small error here... DRAM with 128 cycle refresh needs that in 2ms. All > DRAM with 256 cycle refresh I know of needs that in 4ms so we're good > either way with the 5cycle/scanline implementation. Ah right, 128/2ms and 256/4ms are the two main timings from this era. Thanks for the correction. Segher Message was sent through the cbm-hackers mailing listReceived on 2016-10-13 21:00:41
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