Re: cbm 8032 motherboard + 4164

From: Gerrit Heitsch <>
Date: Thu, 13 Oct 2016 22:11:59 +0200
Message-ID: <>
On 10/13/2016 09:29 PM, Segher Boessenkool wrote:
> On Thu, Oct 13, 2016 at 07:03:30PM +0100, smf wrote:
>> On 13/10/2016 15:28, Gerrit Heitsch wrote:
>>> How much of it is spent in the upper and lower border and the vertical
>>> retrace where no memory access happens (not counting an open border
>>> with sprites)? More than 2 ms?
> Yes, and yes.
>>> So in order to make sure that the DRAM is refreshed properly, they
>>> just implemented a refresh counter which does 5 cycles per scan line.
>> I thought upper/lower border was always fetching $3fff? During the side
>> borders it's fetching sprites, so you can't rely on that for refreshing
> It only fetches for active sprites, too.
>> Doing 5 refresh cycles per scanline will take 51 scanlines to read all
>> 256 addresses.
> This is about 3ms btw, so 2ms DRAMs shouldn't work well at all.

Small error here... DRAM with 128 cycle refresh needs that in 2ms. All 
DRAM with 256 cycle refresh I know of needs that in 4ms so we're good 
either way with the 5cycle/scanline implementation.


       Message was sent through the cbm-hackers mailing list
Received on 2016-10-13 21:00:24

Archive generated by hypermail 2.2.0.