Re: final cartridge for vic 20

From: Jim Brain <>
Date: Sat, 12 Sep 2015 01:06:47 -0500
Message-ID: <>
After debugging, I found my initial error (RTL was reading an old file), 
but have not yet been able to get the reset function to work correctly.  
I have distilled the code down to a minimal amount (caveat that my 
Verilog is still freshman level quality):

module test(reset, clock, r_w, data, io2, uart_ce);
inout reset;
input clock;
input r_w;
inout [7:0]data;
input io2;
output uart_ce;

wire [3:0] cart_config1;
assign uart_ce = 0;
assign reg_write = (!r_w & !io2);
assign data = (r_w & !io2 & clock ? {4'b0,cart_config1} : 8'bz);

reg soft_reset = 0;
always @(negedge clock) soft_reset <= (reg_write & data[7]);

assign reset    =                (soft_reset ? 0 : 1'bz);

register #(.WIDTH(4))    cart_config1_reg(clock, 0, reg_write, 
{data[3:0]}, cart_config1);


and register is defined as:

module register(clock, reset, enable, d, q);

parameter WIDTH = 8 ;
parameter RESET = 0 ;

input clock;
input reset;
input enable;
inout [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] q;

always @ (negedge clock, posedge reset)
         q <= RESET;
   else if(enable)
        q <= d;

As you can see, the reset line on the register parm list is defined as 
0, and I see that in the RTL.  Still, a softreset will reset the 
register to 0.  In short, I am stumped.  VIC RESET is wired to the 
XC95144XL GSR (global reset line), but RTL does not show reset coming 
into the register, and the fitter report does not call out GSR being 
used as a global reset (because reset is gated, I would guess).

Obviously, very frustrating.


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Received on 2015-09-12 07:00:07

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