On 9/9/2015 12:53 PM, Nate Lawson wrote: > If you have any questions, feel free to post it. Depending on the CPLD type you’re using, you can often restructure equations to take advantage of the cell structure and combine multiple terms into a single one. > > -Nate > >> On Sep 9, 2015, at 10:19 AM, Jim Brain <firstname.lastname@example.org> wrote: >> >> I worked a bit on the Verilog last night. >> >> As usual, running out of macrocells on the CPLD, but the registers I have right now are: > > Message was sent through the cbm-hackers mailing list I have placed the Verilog at jbrain.com/incoming/UltiMem_v01.zip Notes: * Target is xc95144xl10-tc100 * It currently synthesizes, but uses all 144 macrocells. I would like a bit more buffer, as there is no support to trigger an IRQ on button press, nor any way to debounce the switches. * The archive does not have the UCF pin constraints file, but I can add it if needed * I am using ISE 14.6 * I can send the full project if needed * Things yet to do: o restructure the code to use the new Verilog parm passing methodology .parm_name[value] or something like that. o Try to restructure MemExpander so the bank width is configurable via a parm Feedback appreciated. Jim -- Jim Brain email@example.com www.jbrain.com Message was sent through the cbm-hackers mailing listReceived on 2015-09-19 07:00:07
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