Re: final cartridge for vic 20

From: Jim Brain <brain_at_jbrain.com>
Date: Fri, 11 Sep 2015 21:08:03 -0500
Message-ID: <55F38903.4040207@jbrain.com>
On 9/11/2015 4:30 PM, Nate Lawson wrote:
>> On Sep 10, 2015, at 7:28 AM, Greg King <greg.king5@verizon.net> wrote:
>>
>> On 2015-09-10 1:24 AM, Jim Brain wrote:
>>> On 9/10/2015 12:11 AM, Nate Lawson wrote:
>>>> I think the problem is here:
>>>>
>>>> ###
>>>> assign reset_in =                (reset_en ? 0 : !reset); //if soft
>>>> reset, 0, otherwise !reset
>>>> register #(.WIDTH(6))                cart_config1_reg(clock, reset_in,
>>>> cart_config1_reg_ce, data[5:0], cart_config1);  // active high reset.
>>>> ###
>>>>
>>>> If the external reset line goes low (which it does when you set
>>>> reset_en to do a soft reset), reset_in goes high and the config
>>>> register is reset. Just stop passing reset_in to the config register
>>>> and get it from a different source.
>>> If external reset lines goes low, but I did so with the soft reset
>>> functionality, then reset_in will be 0, according to the above.  It will
>>> be that way until the next falling clock, given the always block.
>> When is the reset line released?  Does it happen _before_ that falling clock?
The reset line would indeed be released on the next falling clock.
> Yes, I agree. Continuous assignment, wires, etc. arenít registered, so 
> you have to be sure about relative timing of the signals. Personally, 
> Iím not comfortable with using continuous logic from external sources 
> until itís been registered on a clock edge. Thereís too much potential 
> for glitches from ringing etc.
Fair enough.

As I am debugging the code, I have come to a different conclusion, but I 
am not sure how to debug it, as I think it requires someone to look at 
the Verilog in entirety.

On a hunch, I removed reset_in from all of the registers, so no reset 
would ever happen.  But, when I synthesize, the RTL has all register 
reset assigned to !reset, so I am at a loss as to why the connection is 
being made (literally, I put 0 in all register parm lists for the reset 
signal).

I see no reason why the inverter should be there, but I am still 
debugging.  Happy to post the code somewhere for others to peruse...

jim



-- 
Jim Brain
brain@jbrain.com
www.jbrain.com


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Received on 2015-09-12 03:00:07

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