On 7/18/2014 2:18 PM, email@example.com wrote: >> And, I was able to dump out the entire 2kB of ROM. I also found out >> that it looks like the system requires 4 cycles after RESET goes high to >> start, and there needs to be some time while RESET is low to put things >> in order. > How do we define "high" and "low" here? Is "high" 5 or 10? Is "low" 5 or 0? > > In other words could you say bit more on the timing? Like at which cycles should what transitions happen? I felt the transitions should happen on CLKext/2 (in other works, when the incoming clock falls for the 2nd time or 4th time, etc. In the above, high means 5-10V (CPU running, either in regular or test mode), and low means 0v. I found that if I put the system into RESET for internal clock periods (8 external cycles) and then put the system into test mode, the system came up correctly, but if I drove the system into TEST mode right after applying CLOCK and I did not run the CPU through a reset mode, it would not run my program correctly. Message was sent through the cbm-hackers mailing listReceived on 2014-07-19 01:01:38
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