On 7/18/2014 2:33 PM, Gerrit Heitsch wrote: > > > As long as you do it in a way that the date is stable when the CPU > samples it (falling edge of its clock/PHI2 if I remember right), > everything will work and the exact timing is not relevant as long as > the time between command bytes is 2 periods of the external clock. So > safe points are rising and falling edge of 1, 3, 5 and falling edge of > 2 and 4. The rising edge of 2 and 4 would be the problematic part > where the data might not be stable. The safest way would be in the > middle of the HIGH or LOW portion of the external clock, that should > always work. Together with the rather slow clockspeed supplied (250 > KHz external clock?), it should be stable at the sampling moment. I chose 250kHz, knowing that the minimum was 100kHz internal (200kHz external), and I wanted a bit of a buffer. I did try to slow the clock down, but it died slightly below 250kHz, so I think 250kHz is the effective minimum. Jim Message was sent through the cbm-hackers mailing listReceived on 2014-07-19 01:02:07
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