Re: ROM Dump of Amiga Keyboard controller

On 2014-07-19 02:23, Jim Brain wrote:

>>> And, I was able to dump out the entire 2kB of ROM. I also found out
>>> that it looks like the system requires 4 cycles after RESET goes high to
>>> start, and there needs to be some time while RESET is low to put things
>>> in order.
>> How do we define "high" and "low" here? Is "high" 5 or 10? Is "low" 5
>> or 0?
>>
>> In other words could you say bit more on the timing? Like at which
>> cycles should what transitions happen?
> I felt the transitions should happen on CLKext/2  (in other works, when
> the incoming clock falls for the 2nd time or 4th time, etc.
> 
> In the above, high means 5-10V (CPU running, either in regular or test
> mode), and low means 0v.  I found that if I put the system into RESET
> for internal clock periods (8 external cycles) and then put the system
> into test mode, the system came up correctly, but if I drove the system
> into TEST mode right after applying CLOCK and I did not run the CPU
> through a reset mode, it would not run my program correctly.

So the thing is as follows:

1. t=0, RESET to GND
2. 8 CLKext cycles (using 4 "send_data()" calls)
3. RESET to 10V
4. 8 CLKext cycles (using 4 "send_data()" calls)
5. Feed the 6502 "loader" code in a loop
6. Send JMP to "dumper" code (JMP $0000)
7. RESET to 5V
8. Watch the strobe and sip off the data, passing it to UART

But inside the "loader" code loop you have two additional toggles
between TEST and NORMAL mode with "extra cycle" inbetween. What was this
needed for? If I understand correctly - the 6500 should be able to
*store* to its RAM while running in TEST mode, shouldn't it?

-- 
SD!

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