On 07/02/2014 04:06 PM, David Wood wrote: > Considering the minimum clock rate, it's entirely possible to stall the > clock long enough to get from 0v to 10v on /reset before a clock cycle > completes. > > By the way, these NOP loops are getting pretty long, would it make sense > to use a JMP at the end of the loop to avoid having the internal address > bus loop into onboard device or ram locations? The NOPs are just for the beginning so we get everything into a defined state no matter what gets interrupted when RESET goes to +10V. They can probably be shortened. Also, I think we can dispense with the 3 byte BIT command and just use the zero page version together with a NOP for syncing up. But for the moment we should leave it in place since it doesn't hurt. And this is only a bit of test code. Once we figure out what is wrong and get it to run, all it does is set PORT D to $55 and then uses one of the killer opcodes to stop the CPU so PORT D remains stable. Once this runs reliably, we can think about the ROM dump code to load into RAM and how to start it. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2014-07-02 17:00:02
Archive generated by hypermail 2.2.0.