Considering the minimum clock rate, it's entirely possible to stall the clock long enough to get from 0v to 10v on /reset before a clock cycle completes. By the way, these NOP loops are getting pretty long, would it make sense to use a JMP at the end of the loop to avoid having the internal address bus loop into onboard device or ram locations? -David On Wed, Jul 2, 2014 at 9:20 AM, Marko MÃ¤kelÃ¤ <email@example.com> wrote: > On Wed, Jul 02, 2014 at 02:07:37PM +0100, KajtÃ¡r Zsolt wrote: > >> The interrupt disable flag is set on any interrupts by default (including >> reset). What's the reason to have SEI in there then? >> > > Good point. Only if the internal firmware resets the flag with CLI or PLP > very early, it could be needed. For example, if you first release RESET > from 0V to 5V, and then to 10V. > > Anyway, I do not see why using 0x78 instead of 0xea for the padding bytes > would cause any damage. > > Marko > > > Message was sent through the cbm-hackers mailing list > Message was sent through the cbm-hackers mailing listReceived on 2014-07-02 15:00:03
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