> Remember that the external clock is divided by 2 internally and that > the datasheet claims that minimum clock is 200 kHz. Ohh, you are right. That's a third problem. How to detect the right state of the phi2 signal generated from the clock signal. Martin Message was sent through the cbm-hackers mailing listReceived on 2014-06-10 19:01:47
Archive generated by hypermail 2.2.0.