On 06/10/2014 08:12 PM, Martin Hoffmann-Vetter wrote: >> Remember that the external clock is divided by 2 internally and that >> the datasheet claims that minimum clock is 200 kHz. > > Ohh, you are right. That's a third problem. How to detect the right state of > the phi2 signal generated from the clock signal. You might not have to besides making sure that you feed bytes to Port PC at half the clock speed (remember padding bytes for write accesses and dummy accesses done by the 6502) since it only counts what it finds on the port when PHI2 goes low internally. It shouldn't matter whether the Byte it reads has been there for the full cycle or only half of it. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2014-06-10 19:02:37
Archive generated by hypermail 2.2.0.