On 04/28/2014 10:40 PM, smf wrote: > >> Yes, but why exactly? The CPU has handed the value (whatever it is) to >> the register hundreds of ns before VIC puts his addresses on the bus. >> Everything should be stable by then. Why isn't it? And this only >> happens on some VICs, others don't have that problem. > > VIC assumes certain things have been done in previous cycles based on > what it knows now. Which is pretty much how all the VIC effects work > (opening the borders etc). The way I understand it, the timing inside VIC is mostly generated by counters and comperators that kick off actions when a counter reaches a certain value. I understand what happens on the outside, what I'm interested in is what happens inside VIC, meaning what part of the logic misfires that long after all the registers have been loaded. Gerrit Message was sent through the cbm-hackers mailing listReceived on 2014-04-28 21:07:52
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