Re: 'Frankenstein' Disk Drives, Done Cheap

>I understand what happens on the outside, what I'm interested in is what 
>happens inside VIC, meaning what part of the logic misfires that long after 
>all the registers have been loaded.

lft covers it pretty comprehensively.

http://www.linusakesson.net/scene/safevsp/

"The C64 accesses memory twice in every clock cycle. Each memory access 
begins with the LSB of the address (also known as the row address) being 
placed on an internal bus connected to the DRAM chips. As soon as the row 
address is stable, the row address strobe (RAS) signal is given. Each DRAM 
chip now latches the row address into a register, and this register controls 
a multiplexer which connects the selected memory row to a set of wires 
called sense lines. Each sense line connects to a single bit of memory.

The sense lines have been precharged to a voltage in between logical zero 
and logical one. The charge stored in the memory cell affects the sense line 
towards a slightly lower or higher voltage depending on the bit value. A 
feedback amplifier senses the voltage difference and exaggerates it, so that 
the sense line reaches the proper voltage representing either zero or one. 
Because the memory cell is connected (through the multiplexer) to the sense 
line, the amplified charge will also flow back and refresh the memory cell. 
Hence, a memory row is refreshed whenever it is opened.

VSP is achieved by triggering a badline condition during idle mode in the 
visible part of a rasterline. When this happens, the VIC chip gets confused 
about what memory address to access during the half-cycle following the 
write to $d011. It sets the internal bus lines to 11111111 in preparation 
for an idle fetch, but suddenly changes its mind and tries to read from an 
address with an LSB of 00000111. "

I think someone would need to decap and draw out schematics to get any 
better understanding about how VIC handled it internally. My guess is that 
there is something equivalent to:

while (1)
{
    if ((*d011)&7 == rasterline && !badline)
    {
       badline = 1;
       dobadline();
    }
    ......
    if (startofrasterline())
        rasterline++;
        rasterline&=7;
}

and the designers assumed that the first condition only becomes true when 
rasterline++ happens, so it would be at the start of a line. However 
changing d011 can make it happen at any time on a line, if you do it during 
idle then it goes haywire (which is what allows VSP to work). 


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