Re: More CPLD explorations

From: Nate Lawson <>
Date: Wed, 26 Feb 2014 23:35:40 -0800
Message-Id: <>
On Feb 26, 2014, at 8:13 AM, Gerrit Heitsch <> wrote:

> On 02/25/2014 09:44 PM, wrote:
>> On 2014-02-25 at 20:49:07, Gerrit Heitsch ( wrote:
>>> The fun part is, if you look at a chip itself and measure just between
>>> +5V and GND of that chip, everything is a bit noisy, but not really
>>> bad.
>>> It's just that the ends of the board in relation to each other do
>>> funny
>>> things. The 1V peak-to-peak is only a few ns, and a half cycle is
>>> about 500ns.
>> Well, this doesn’t mean such thing can be “written off” due to the length of the pulses. Of course it depends on various things but it still can be a disruptive factor for regular operations even if those are short.
> Also, remember, the image I mailed you shows the difference in GND potential between the 2 points far away from each other. When you take a closer look at Vcc and GND on each IC, it's still noisy, but a lot less so.

Sounds like ground bounce, possibly solvable by finding the responsible line drivers and providing decoupling caps.


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Received on 2014-02-27 08:00:13

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